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FPGA入门实验篇之VGA篇
网友 问题 日期
【问】欧阳紫嫣 总是在网站中看到FPGA技术,翻译是现场可编程门阵列 但一直不明白到底哪里用到这个FPGA,该不该学习 2014-07-15 19:04:26
【答】 这个问题暂时没有人回答呦!
【问】xqh518 请问:这是直接接显示器还是前级驱?谢谢 2014-07-08 20:10:27
【答】 这个问题暂时没有人回答呦!
【问】张小瓜 性能如何?还有价位 2014-07-06 08:14:59
【答】 这个问题暂时没有人回答呦!
【问】SYD2012 学习i 了 2014-07-05 23:13:41
【答】 这个问题暂时没有人回答呦!
【问】bruceleesohu xuexi! 2014-06-25 17:11:28
【答】 这个问题暂时没有人回答呦!
【问】573181735 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- the vga_controller_640_60 entity declaration -- read above for behavioral description and port definitions. entity vga_controller_640_60 is port( rst : in std_logic; pixel_clk : in std_logic; HS : out std_logic; VS : out std_logic; hcount : out std_logic_vector(10 downto 0); vcount : out std_logic_vector(10 downto 0); blank : out std_logic ); end vga_controller_640_60; architecture Behavioral of vga_controller_640_60 is ------------------------------------------------------------------------ -- CONSTANTS ------------------------------------------------------------------------ -- maximum value for the horizontal pixel counter constant HMAX : std_logic_vector(10 downto 0) := "01100100000"; -- 800 -- maximum value for the vertical pixel counter constant VMAX : std_logic_vector(10 downto 0) := "01000001101"; -- 525 -- total number of visible columns constant HLINES: std_logic_vector(10 downto 0) := "01010000000"; -- 640 -- value for the horizontal counter where front porch ends constant HFP : std_logic_vector(10 downto 0) := "01010001000"; -- 648 -- value for the horizontal counter where the synch pulse ends constant HSP : std_logic_vector(10 downto 0) := "01011101000"; -- 744 -- total number of visible lines constant VLINES: std_logic_vector(10 downto 0) := "00111100000"; -- 480 -- value for the vertical counter where the front porch ends constant VFP : std_logic_vector(10 downto 0) := "00111100010"; -- 482 -- value for the vertical counter where the synch pulse ends constant VSP : std_logic_vector(10 downto 0) := "00111100100"; -- 484 -- polarity of the horizontal and vertical synch pulse -- only one polarity used, because for this resolution they coincide. constant SPP : std_logic := '0'; ------------------------------------------------------------------------ -- SIGNALS ------------------------------------------------------------------------ -- horizontal and vertical counters signal hcounter : std_logic_vector(10 downto 0) := (others => '0'); signal vcounter : std_logic_vector(10 downto 0) := (others => '0'); -- active when inside visible screen area. signal video_enable: std_logic; begin -- output horizontal and vertical counters hcount <= hcounter; vcount <= vcounter; -- blank is active when outside screen visible area -- color output should be blacked (put on 0) when blank in active -- blank is delayed one pixel clock period from the video_enable -- signal to account for the pixel pipeline delay. blank <= not video_enable when rising_edge(pixel_clk); -- increment horizontal counter at pixel_clk rate -- until HMAX is reached, then reset and keep counting h_count: process(pixel_clk) begin if(rising_edge(pixel_clk)) then if(rst = '1') then hcounter <= (others => '0'); elsif(hcounter = HMAX) then hcounter <= (others => '0'); else hcounter <= hcounter + 1; end if; end if; end process h_count; -- increment vertical counter when one line is finished -- (horizontal counter reached HMAX) -- until VMAX is reached, then reset and keep counting v_count: process(pixel_clk) begin if(rising_edge(pixel_clk)) then if(rst = '1') then vcounter <= (others => '0'); elsif(hcounter = HMAX) then if(vcounter = VMAX) then vcounter <= (others => '0'); else vcounter <= vcounter + 1; end if; end if; end if; end process v_count; -- generate horizontal synch pulse -- when horizontal counter is between where the -- front porch ends and the synch pulse ends. -- The HS is active (with polarity SPP) for a total of 96 pixels. do_hs: process(pixel_clk) begin if(rising_edge(pixel_clk)) then if(hcounter >= HFP and hcounter < HSP) then HS <= SPP; else HS <= not SPP; end if; end if; end process do_hs; -- generate vertical synch pulse -- when vertical counter is between where the -- front porch ends and the synch pulse ends. -- The VS is active (with polarity SPP) for a total of 2 video lines -- = 2*HMAX = 1600 pixels. do_vs: process(pixel_clk) begin if(rising_edge(pixel_clk)) then if(vcounter >= VFP and vcounter < VSP) then VS <= SPP; else VS <= not SPP; end if; end if; end process do_vs; -- enable video output when pixel is in visible area video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0'; end Behavioral; 这个引脚怎么分配 芯片是EPM240T100C5N 2014-03-11 17:02:49
【答】 这个问题暂时没有人回答呦!
【问】573181735 我用的cpld epm240t100c5n 引脚怎么分配啊 ,vhdl语言中定义hcount : out std_logic_vector(10 downto 0); vcount : out std_logic_vector(10 downto 0); 2014-03-11 17:01:55
【答】 这个问题暂时没有人回答呦!